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irqbalance: update to version 1.9.4

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This commit is contained in:
coolsnowwolf 2025-01-19 15:30:36 +08:00
parent 066f927aa3
commit b8546f758e
4 changed files with 8 additions and 73 deletions
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6
utils/irqbalance/Makefile
View File

@ -5,13 +5,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=irqbalance
PKG_VERSION:=1.9.2
PKG_RELEASE:=2
PKG_VERSION:=1.9.4
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/Irqbalance/irqbalance.git
PKG_SOURCE_VERSION:=v$(PKG_VERSION)
PKG_MIRROR_HASH:=e2c81725e7b6d711a47d68755a222236d7081726d567aca1c1295e6fe1caa865
PKG_MIRROR_HASH:=92af1d0e6775e1b66bc34da95443d9f2d953ec0c3c276dc55f9558029f9c42b8
PKG_MAINTAINER:=Hannu Nyman <hannu.nyman@iki.fi>
PKG_LICENSE:=GPL-2.0-or-later

2
utils/irqbalance/files/irqbalance.config
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@ -1,5 +1,5 @@
config irqbalance 'irqbalance'
option enabled '0'
option enabled '1'
# Level at which irqbalance partitions cache domains.
# Default is 2 (L2$).

68
utils/irqbalance/patches/001-upstream-fix-aarch64-irq-parsing.patch
View File

@ -1,68 +0,0 @@
From bbcd9a42c3cec0935b960b7f2046f1fdfab4f7ef Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Wed, 7 Dec 2022 19:46:19 +0530
Subject: [PATCH] procinterrupts: Fix IRQ name parsing on certain arm64 SoC
On arm64 SoCs like TI's K3 SoC and few other SoCs, IRQ names don't get
parsed correct due to which they end up being classified into wrong
class. Fix this by considering last token to contain IRQ name always.
Eg.: /proc/interrupt
cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 7155 8882 7235 7791 GICv3 30 Level arch_timer
14: 0 0 0 0 GICv3 23 Level arm-pmu
15: 0 0 0 0 GICv3 208 Level 4b00000.spi
16: 0 0 0 0 GICv3 209 Level 4b10000.spi
116: 0 0 0 0 MSI-INTA 1716234 Level 485c0100.dma-controller chan6
134: 166 0 0 0 MSI-INTA 1970707 Level 8000000.ethernet-tx0
224: 149 0 0 0 MSI-INTA 1971731 Level 8000000.ethernet
W/o patch irqbalance -d
IRQ (11) guessed as class 0
IRQ (14) guessed as class 0
IRQ (15) guessed as class 0
IRQ (16) guessed as class 0
IRQ 485c0100.dma-controller chan6(116) guessed as class 0
IRQ (134) guessed as class 0
IRQ (224) guessed as class 0
W/ this patch
IRQ arch_timer(11) guessed as class 0
IRQ arm-pmu(14) guessed as class 0
IRQ 4b00000.spi(15) guessed as class 0
IRQ 4b10000.spi(16) guessed as class 0
IRQ 485c0100.dma-controller chan6(116) guessed as class 0
IRQ 8000000.ethernet-tx0(134) guessed as class 5
IRQ 8000000.ethernet(224) guessed as class 5
IRQ 8000000.ethernet(257) guessed as class 5
IRQ -davinci_gpio wl18xx(362) guessed as class
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
procinterrupts.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
--- a/procinterrupts.c
+++ b/procinterrupts.c
@@ -178,12 +178,14 @@ void init_irq_class_and_type(char *saved
}
#ifdef AARCH64
- if (savedptr && strlen(savedptr) > 0) {
+ if (savedptr && strlen(savedptr) > 0)
snprintf(irq_fullname, PATH_MAX, "%s %s", last_token, savedptr);
- tmp = strchr(irq_fullname, '\n');
- if (tmp)
- *tmp = 0;
- }
+ else
+ snprintf(irq_fullname, PATH_MAX, "%s", last_token);
+
+ tmp = strchr(irq_fullname, '\n');
+ if (tmp)
+ *tmp = 0;
#else
snprintf(irq_fullname, PATH_MAX, "%s", last_token);
#endif

5
utils/irqbalance/patches/010-meson.patch
View File

@ -4,6 +4,9 @@ Date: Fri, 10 Jun 2022 23:14:27 -0700
Subject: [PATCH] add meson
Signed-off-by: Rosen Penev <rosenp@gmail.com>
[update version string to 1.9.4]
---
meson.build | 43 +++++++++++++++++++++++++++++++++++++++++++
meson_options.txt | 11 +++++++++++
@ -15,7 +18,7 @@ Signed-off-by: Rosen Penev <rosenp@gmail.com>
+++ b/meson.build
@@ -0,0 +1,43 @@
+project('irqbalance', 'c',
+ version : '1.9.0',
+ version : '1.9.4',
+ default_options : ['warning_level=1']
+)
+